Field of the Invention
This invention relates generally to memory systems, and more particularly to memory systems which include a memory buffer that serves as an interface between a host controller and the RAM chips residing on a DIMM.
Description of the Related Art
Traditional computer systems, such as servers, workstations, desktops and laptops, all use pluggable memory which can be inserted into slots on the computer's motherboard as needed. The most common form of pluggable memory is the DIMM. Historically, DIMMs contain multiple RAM chips—typically DRAM—each of which has a data bus width of 4 or 8 bits. Typically, eight or nine 8-bit DRAM chips (or twice as many 4-bit DRAM chips) are arranged in parallel to provide each DIMM with a total data bus width of 64 or 72 bits; the data bus, typically referred to as the ‘DQ’ bus, is connected to a host controller. Each arrangement of 64 or 72 data bits using DRAM chips in parallel is termed a ‘rank’.
A command/address (CA) bus also runs between the host controller and each DIMM; the CA and DQ busses together form a ‘system’ bus. With a basic unbuffered DIMM, the CA bus is connected to every DRAM on the DIMM. As a result, there is a high electrical load on the CA bus, given by the product of the number of DRAMs times the number of ranks. For the DQ bus, the number of electrical loads is equal to the number of ranks.
A buffering device is employed to reduce loading in a ‘load reduction’ DIMM (LR-DIMM), an example of which is illustrated in FIG. 1. An LR-DIMM 14 containing multiple DRAM chips 12 uses a logic device 10 to buffer the DQ and CA signals between the DRAMs and a host controller 16. Logic device 10 may be, for example, a single device such as the iMB (isolating Memory Buffer) from Inphi Corporation. Memory systems of this sort are described, for example, in co-pending U.S. patent application Ser. Nos. 12/267,355 and 12/563,308, which are incorporated herein by reference.